Synopsys is hiring FRESHERS for Intern-Technical profile
Fresh BSEE graduate Or 1 to 2 yrs of s/w testing intern experience.
Knowledge in Verilog/VHDL ,TCL language ,Shell scripting ,Linux/UNIX (Desirable)
Knowledge in Testing of S/W tools (Desirable)
Company Name: Synopsys
Responsible for testing Synopsys FPGA Synthesis core products.
This gives the chance to be in the cutting edge technology in FPGA synthesis and prototyping and to become an expert in many high tech Synopsys tools.
In this role you will be assuming the complete responsibility of testing the GUI.
You will also be creating automated test cases using squish for GUI related features for synthesis tools.
You would be required to analyze and fix regressions tests.
Synopsys is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, IP and services used in semiconductor design and manufacturing. Synopsys’ comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and FPGA solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results.
How to Apply:
CLICK HERE TO APPLY FOR THIS JOB