Synopsys is hiring FRESHERS for Intern-Technical profile
Graduate/Post graduate student in CS/EC with excellent C programming skills, thorough in Data Structures and Algorithms and good Digitial Design knowledge.
Knowledge of PERL, Tcl and Shell scripting; debugger(gdb); HDLs like VHDL/Verilog are an added advantage.
Should be a self learner, committed, good team player with good written/oral communication skills.
Company Name: Synopsys
This Engineer will contribute towards improving the Quality of Design Compiler, Synopsys’ industry-leading RTL Synthesis Tool.
The engineer will work on tasks such as, fixing memory related issues, improving the code coverage, fixing compile warnings.
Development will be in C. The engineer will require to perform first level debugging on any issues hit during development, using standard tools available in-house.
As part of the job, the engineer will also design and develop testcases in VHDL/Verilog to test the features/bugs fixed by the individual.
The engineer will also be responsible to validate the code changes across the existing Regression testing system and QoR suite.
The engineer will have to adhere by the standard practices followed such as code review, testing the code through purify, testing across multiple platforms etc.
Synopsys is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, IP and services used in semiconductor design and manufacturing. Synopsys’ comprehensive, integrated portfolio of implementation, verification, IP, manufacturing and FPGA solutions helps address the key challenges designers and manufacturers face today, such as power and yield management, system-to-silicon verification and time-to-results.
How to Apply: